SoC Limits Management Lead

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a SoC Limits Management Lead in the System Power and Performance team, you will be responsible for defining how our next-generation systems balance high performance against physical and electrical constraints. You will bridge the gap between hardware IP, system software, and product requirements to design a holistic "Limits Management" subsystem. Your work ensures our SoCs deliver maximum performance under peak current constraints, while maintaining long-term reliability and stability.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $240000 - $334000 (USD) + 25% bonus target + equity + benefits

Learn more about [benefits at Google](https://www.google.com/about/careers/applications/benefits/).

Responsibilities

• Define the SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
• Lead cross-functional teams to standardize critical mitigation features, including Power Telemetry, Estimators, and Droop Detectors, across all IP and hardware blocks.
• Drive the long-term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms to address escalating current densities and industry trends.
• Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for various mitigation strategies.
• Drive organizational consensus on feature return on investment (ROI) and oversee Post-Silicon Validation to ensure physical silicon behavior aligns with architectural intent.