Senior FPGA Design Verification Engineer

Company Description

It started with a simple idea: what if surgery could be less invasive and recovery less painful? Nearly 30 years later, that question still fuels everything we do at Intuitive. As a global leader in robotic-assisted surgery and minimally invasive care , our technologies—like the da Vinci surgical system and Ion —have transformed how care is delivered for millions of patients worldwide. We’re a team of engineers, clinicians, and innovators united by one purpose: to make surgery smarter, safer, and more human. Every day, our work helps care teams perform with greater precision and patients recover faster, improving outcomes around the world. The problems we solve demand creativity, rigor, and collaboration. The work is challenging, but deeply meaningful—because every improvement we make has the potential to change a life. If you’re ready to contribute to something bigger than yourself and help transform the future of healthcare , you’ll find your purpose here.

Job Description

Roles & Responsibilities

• Verification of FPGA’s on daVinci systems for RTL functional correctness
• Starting from test-planning to closing verification using coverage metrics
• Hands-on testbench development UVM
• Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model
• Write constrained random stimulus and Implement functional cover groups
• Debugging failures, bug tracking, and analyze and close coverage

Qualifications

Required Education, Skills & Experience

• Advanced knowledge of HVL methodology (UVM)
• Expertise in HVL and HDL (SystemVerilog, Verilog)
• Experience defining coverage space and writing coverage models
• Team player with excellent communication skills and the desire to take on diverse challenges
• Experience writing scripts in languages such as Perl/Python
• Solid verification skills in problem solving, constrained random testing, and debugging
• Experience with Emulation/FPGA prototyping and Formal is a plus
• Experience with ML-assisted flows, and agentic-AI automation frameworks to accelerate coverage closure, improve debug efficiency, and enhance overall verification throughput